1. Field of the Invention
The present invention relates to an image sensor, and more particularly, to a CMOS image sensor capable of reducing a leakage current by gettering metal ion contamination by implanting p type impurity ions in a dummy moat region and a method of manufacturing the CMOS image sensor.
2. Description of the Related Art
In general, image sensors are a semiconductor device for converting an optical image to an electrical signal. Among the image sensors, a charge coupled device (CCD) is a device in which individual MOS (Metal-Oxide-Silicon) capacitors are closely disposed to each other, and charge carriers are stored in the capacitors.
A CMOS image sensor is a switching type device in which MOS transistors corresponding to the number of pixels are formed by using a CMOS technique employing a control circuit and a signal processing circuit as peripheral circuits and outputs are sequentially detected.
In the CCD device the driving mechanism is complicated and power consumption is large. In addition, since the number of mask process steps is large, the process to fabricate it is complicated. Since a signal processing circuit cannot be disposed in the CCD chip, it is also difficult to form the CCD device in form of one Chip. Recently, in order to solve the aforementioned problems, a CMOS image sensor using a sub-micron CMOS manufacturing technique has been researched and developed.
The CMOS image sensor is constructed by disposing a photodiode and a MOS transistor in each of unit pixels and sequentially detects signals in the switching scheme to form an image. Since the CMOS manufacturing technique is used, power consumption is small. In addition, since the number of masks is about 20, the process is very simple in comparison to the CCD process requiring 30 to 40 masks. Various signal processing circuits can be constructed on one chip. Therefore, attention has been paid to the CMOS image sensor as a next-generation image senor. The CMOS image sensor has been widely used in many applications such as DSCs (Digital Still Cameras), PC cameras, and mobile cameras.
A conventional method of a CMOS image sensor will now be described in detail with reference to the accompanying drawings.
FIGS. 1A to 1G are cross sectional views of a semiconductor device showing a conventional method manufacturing a CMOS image sensor.
As shown in FIG. 1A, element isolation films 32 are formed in a field region of a semiconductor substrate 31 having an active region, the field region, and a dummy moat region.
Here, the element isolation film 32 is formed by using an STI (Shallow Trench Isolation) process for etching the field region of the semiconductor substrate 31 in a predetermined depth to form a trench and burying an insulating material in an inner portion of the trench.
The active region includes a PMOS transistor region and a NMOS transistor region, and a photodiode region is defined in the NMOS transistor region.
Next, a photodiode 33 is formed by implanting impurity ions having a conductivity type opposite to that of the semiconductor substrate 31 in the photodiode region of the semiconductor substrate 31.
Next, after a first photosensitive film 34 is applied on the entire surface of the semiconductor substrate 31, the first photosensitive film 34 is patterned so as to mask the PMOS transistor region excluding the NMOS transistor region the dummy moat region by using exposing and developing processes.
Subsequently, by using the patterned first photosensitive film 34 as a mask, p type impurity ions are implanted in the entire surface of the semiconductor substrate 31 to form a P-well region 35 in the NMOS transistor region and the dummy moat region.
As shown in FIG. 1B, the first photosensitive film 34 is removed, and after a second photosensitive film 36 is applied to the entire surface of the semiconductor substrate 31, the second photosensitive film 36 are selectively patterned so as to open the PMOS transistor region by using exposing and developing processes.
Next, by using the patterned second photosensitive film 36 as a mask, n type impurity ions are implanted in the PMOS transistor region to form the N-well region 37.
As shown in FIG. 1C, after the second photosensitive film 36 is removed, a gate insulating film 38 and a gate-electrode polysilicon film are sequentially formed on the semiconductor substrate 31.
Next, the poly silicon film and the gate insulating film 38 are selectively etched to form a gate electrode 39 in the semiconductor substrate 31 in the PMOS transistor region and the NMOS transistor region.
Next, after a third photosensitive film 40 is applied on the semiconductor substrate 31, the third photosensitive film 40 are selectively patterned so as to open the NMOS transistor region and the dummy moat region by using exposing and developing processes.
Next, by using the patterned third photosensitive film 40 as a mask, n type impurity ions are implanted in the P-well region 35 and the dummy moat region to form a lightly doped n type impurity region 41.
As shown in FIG. 1D, the third photosensitive film 40 is removed, and after a fourth photosensitive film 42 is applied to the entire surface of the semiconductor substrate 31, the fourth photosensitive film 42 is selectively patterned so as to open the PMOS transistor region by using exposing and developing processes.
Next, by using the patterned fourth photosensitive film 42 as a mask, lightly doped p type impurity ions are implanted in the N-well region 37 to form a lightly doped p type impurity region 43.
As shown in FIG. 4E, the fourth photosensitive film 42 is removed, and after an insulating film is deposited on the entire surface of the semiconductor substrate 31, an etchback process is performed to form insulating film sidewalls 44 on both sides of the gate electrode 39.
Next, after a fifth photosensitive film 45 is applied to the entire surface of the semiconductor substrate 31, the fifth photosensitive film 45 is selectively patterned so as to open the NMOS transistor region by using exposing and developing processes.
Subsequently, by using the patterned fifth photosensitive film 45 as a mask, heavily doped n type impurity ions (for example, As) are implanted in the P-well region 35 and the dummy moat region to form the heavily doped n type impurity region 46 and an N+ region 47 simultaneously.
As shown in FIG. 1F, the fifth photosensitive film 45 is removed, and after a sixth photosensitive film 48 is applied to the entire surface of the semiconductor substrate 31, the sixth photosensitive film 48 is selectively patterned so as to open the PMOS transistor region and the dummy moat region by using exposing and developing processes.
Next, by using the patterned sixth photosensitive film 48 as a mask, heavily doped p type impurity ions are implanted in the N-well region 37 to form the heavily doped p type impurity region 49.
As shown in FIG. 1G, after the sixth photosensitive film 48 is removed, a thermal treatment process is performed on the semiconductor substrate 301 to activate the impurity ions implanted in the semiconductor substrate 31.
In the following processes (not shown), a plurality of interlayer insulating films, metal wire lines, color filter layers, and micro lenses are formed on the semiconductor substrate 31, so that an image sensor is manufactured.
In the method of manufacturing the CMOS image sensor in the aforementioned conventional technique, there is the following problem.
Since the heavily doped n type impurity ions are implanted in the dummy moat region, gettering effect for the metal ions is too small to reduce the leakage current.